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Writing and managing Tests

Contents are extracted from the Advanced UVM sessions by Verification Academy.

What is a test?​

The environment is the “testbench”

  • Defines what components are needed to verify the DUT
  • Specifies defaults

The test’s job is to “tweak” the tesbench

  • Configuration
  • Factory overrides
  • Additional sequences

The test’s other job is to ensure that the simulation ends

Defaults in UVM​

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Can add additional check to make sure the value pass by the configuration DB from the test is still legal

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Use a Base Test to set defaults​

There is option to override the environment type, make sure to do factory override before calling super.build inside the extended test

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Extend Base Test to create a Test​

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To override the environment type as mentioned above:

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Set up and invoke test​

Instantiate the DUT’s virtual interface and pass it down to the testbench through UVM config DB

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Complex environment, simple test​

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Simple Test​

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Extended Test​

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The virtual sequence can also be overridden using the set_type_override method → Explicit sequence type override

Managing Test Execution: Phase objections​

Components or Sequences can raise or drop objections

Phase continues until all raised objections are dropped

An objection must be raised at the beginning of the phase

Objections are hierarchical​

Objections are raised up the hierarchy by default

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Sequencer’s objection + Monitor’s objection = 2 agent’s objections

Objections are dropped hierarchically too

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When a component’s count = 0, wait for drain_time to elapse

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Recommendation​

Raise and drop objections inside the test

Allows the test to determine when all the stimulus is complete and start dropping the objection

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There might be cases where the objections is drop before the last transaction hasn’t finish processing yet

Using objections​

Scoreboard recording transactions can raise an objection to prevent the test from ending early, make sure all the transactions has been recorded

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Not recommended since it will introduce additional overhead

Alternative solution:

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Recommendation: Objecting in a component​

Using the provided method phase_ready_to_end to do the objection before ending the phase

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Summary​

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